The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation. Among the feature sizes which are reduced in size are the width and spacing of interconnecting metal lines and the contact openings through which the metallization makes electrical contact to device regions.
One solution for some of these problems is provided in U.S. Pat. No. 6,121,684, incorporated herein by reference. This patent provides an integrated butt contact having a protective spacer. Butted contacts, such as those discussed in the presently incorporated patent, have been adopted in semiconductor memory devices to increase device density by reducing the necessary size of the area for contact purposes. However, since butted contacts are frequently used in combination with square contacts, such a combination causes challenges to lithograph and etch steps. For example, lithograph and etch steps have to accommodate different contact sizes, shapes and loading effects, resulting in frequent defects, such as photo bridge, contact hole blind and/or high junction leakage.
Accordingly, it is desirable to provide an improved connection structure for semiconductor devices.